1. Field
The present invention relates to a liquid crystal display, and more particularly to a thin film transistor substrate of horizontal electric field applying type and a fabricating method thereof that are capable of simplifying processing by using fewer mask processes as well as improving lift-off ability.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) controls light transmittance of liquid crystal disposed therein using an electric field to thereby display a picture. The liquid crystal displays are largely classified into a vertical electric field type and a horizontal electric field type depending upon the direction of the electric field driving the liquid crystal.
The liquid crystal display of vertical electric field applying type drives a liquid crystal in a twisted nematic (TN) mode with a vertical electric field formed between a pixel electrode and a common electrode arranged in opposition to each other on the upper and lower substrate. The liquid crystal display of vertical electric field applying type has a large aperture ratio but also has a narrow viewing angle of about 90°.
The liquid crystal display of horizontal electric field applying type drives a liquid crystal in an in plane switch (IPS) mode with a horizontal electric field between the pixel electrode and the common electrode arranged in parallel to each other on the lower substrate. The liquid crystal display of horizontal electric field applying type has a wide viewing angle of about 160°.
Hereinafter, the liquid crystal display of horizontal electric field applying type will be described in detail.
The liquid crystal display of the horizontal electric field applying type includes a thin film transistor substrate (i.e., a lower substrate) and a color filter substrate (i.e., an upper substrate) joined in opposition to each other, a spacer for uniformly maintaining a cell gap between two substrates, and a liquid crystal filled into the cell gap.
The thin film transistor array substrate is comprised of a plurality of signal wirings for forming a horizontal electric field for each pixel, a plurality of thin film transistors, and an alignment film coated thereon to align the liquid crystal. The color filter substrate includes a color filter for implementing different colors, a black matrix for preventing light leakage and an alignment film coated thereon to align the liquid crystal.
In such a liquid crystal display, the thin film transistor substrate has a complicated fabrication process. This leads to a major rise in the manufacturing costs of the liquid crystal display panel because it involves both semiconductor processes and a plurality of mask processes. Prior thin film transistor substrates have been developed to reduce the number of mask processes. This is because each mask process includes a number of processes such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping and inspection, etc. Although conventional thin film transistor substrates use five mask processes, recently, a thin film transistor substrate using a four-mask process has been introduced.
FIG. 1 is a plan view showing a structure of a thin film transistor substrate of horizontal electric applying type adopting the conventional four-mask process, and FIG. 2 is a section view of the thin film transistor substrate taken along the I-I′ and II-II′ line in FIG. 1.
Referring to FIG. 1 and FIG. 2, the thin film transistor substrate includes a gate line 2 and intersecting a data line 4 provided on a lower substrate 45 with a gate insulating film 46 therebetween, a thin film transistor 6 provided at each intersection, a pixel electrode 14 and a common electrode 18 provided at a pixel area defined by the intersection to form a horizontal field, and a common line 16 connected to the common electrode 18. Further, the thin film transistor substrate includes a storage capacitor 20 provided at an overlapped portion between the pixel electrode 14 and the common line 16, a gate pad 24 connected to the gate line 2, and a data pad 30 connected to the data line 4 and a common pad 36 connected to the common line 16.
The gate line 2 supplied with a gate signal and the data line 4 supplied with a data signal are provided at the intersection to defined a pixel area.
The common line 16 supplied with a reference voltage for driving the liquid crystal is provided parallel to the gate line 2 with the pixel area therebetween.
The thin film transistor 6 allows the pixel signal of the data line 4 to be charged and maintained in the pixel electrode 14 in response to the gate signal of the gate line 2. To this end, the thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, and a drain electrode 12 connected to the pixel electrode 14. Further, the thin film transistor 6 includes an active layer 48 overlapping with the gate electrode 8 with a gate insulating film 46 therebetween to define a channel between the source electrode 10 and the drain electrode 12.
The active layer 48 also overlaps with the data line 4, a lower data pad electrode 32 and an upper storage electrode 22. On the active layer 48, an ohmic contact layer 50 for making ohmic contact with the data line 4, the source electrode 10, the drain electrode 12, and the lower data pad electrode 32 is further provided.
The pixel electrode 14 is connected, via a first contact hole 13 going through a protective film 52, to the drain electrode 12 of the thin film transistor 6 and is provided at the pixel area. Particularly, the pixel electrode 14 includes a first horizontal part 14A connected to the drain electrode 12 and provided in parallel with adjacent gate lines 2, a second horizontal part 14B overlapping with the common line 16, and a finger part 14C provided in parallel between the first and second horizontal parts 14A and 14B.
The common electrode 18 is connected to the common line 16 and is provided in the pixel area. Specifically, the common electrode 18 is provided in parallel with the finger part 14C of the pixel electrode 14 in the pixel area.
Accordingly, a horizontal electric field is formed between the pixel electrode 14, to which a pixel signal is supplied via the thin film transistor 6, and the common electrode 18, to which a reference voltage is supplied via the common line 16. Specifically, the horizontal electric field is formed between the finger part 14C of the pixel electrode 14 and the common electrode 18. Liquid crystal molecules arranged in the horizontal direction between the thin film transistor substrate and the color filter substrate are rotated due to dielectric anisotropy by the horizontal electric field. Transmittance of light through the pixel area depends upon the extent of rotation of the liquid crystal molecules, thereby implementing a gray level scale.
The storage capacitor 20 consists of the common line 16, an upper storage electrode 22 overlapping the common line 16 with the gate insulating film 46, the active layer 48 and the ohmic contact layer 50 therebetween, and a pixel electrode 14 connected, via a second contact hole 21 provided at the protective film 52, to the upper storage electrode 22. The storage capacitor 20 allows a pixel signal charged in the pixel electrode 14 to be stably maintained until the next pixel signal is charged.
The gate line 2 is connected, via the gate pad 24, to a gate driver (not shown). The gate pad 24 consists of a lower gate pad electrode 26 extended from the gate line 2, and an upper gate pad electrode 28 connected, via a third contact hole 27 going through the gate insulating film 46 and the protective film 52, to the lower gate pad electrode 26.
The data line 4 is connected, via the data pad 30, to the data driver (not shown). The data pad 30 consists of a lower data pad electrode 32 extended from the data line 4, and an upper data pad electrode 34 connected, via a fourth contact hole 33 going through the protective film 52, to the lower data pad electrode 32.
The common line 16 receives a reference voltage from an external reference voltage source (not shown) through the common pad 36. The common pad 36 consists of a lower common pad electrode 38 extended from the common line 16, and an upper common pad electrode 40 connected, via a fifth contact hole 39 going through the gate insulating film 46 and the protective film 52, to the lower common pad electrode 38.
A method of fabricating the thin film transistor substrate having the above-mentioned structure using the four mask process procedure will be described in detail with reference to FIGS. 3A to 3D.
Referring to FIG. 3A, a gate metal pattern group including the gate line 2, the gate electrode 8 and the lower gate pad electrode 26, the common line 16, the common electrode 18 and the lower common pad electrode 38 is provided on the lower substrate 45 by the first mask process.
More specifically, a gate metal layer is formed on the upper substrate 45 by a deposition technique such as sputtering. Then, the gate metal layer is patterned by photolithography and the etching process using a first mask to thereby form the gate metal pattern group including the gate line 2, the gate electrode 8, the lower gate pad electrode 26, the common line 16, common electrode 18 and the lower common pad electrode 38. Herein, the gate metal layer is formed from a metal such as aluminum-group metal, chrome (Cr) or molybdenum (Mo).
Referring to FIG. 3B, the gate insulating film 46 is coated onto the lower substrate 45 provided with the gate metal pattern group. Further, a semiconductor pattern including the active layer 48 and the ohmic contact layer 50 and a source/drain metal pattern group including the data line 4, the source electrode 10, the drain electrode 12, the lower data pad electrode 32 and the upper storage electrode 22 are provided on the gate insulating film 46 by the second mask process.
More specifically, the gate insulating film 46, an amorphous silicon layer, a n+ amorphous silicon layer and a source/drain metal layer are sequentially provided on the lower substrate 45 provided with the gate metal pattern group by deposition techniques such as plasma enhanced chemical vapor deposition (PECVD) and sputtering, etc. Herein, the gate insulating film 44 is formed from an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). The source/drain metal is made from molybdenum (Mo), titanium (Ti), tantalum (Ta) or a molybdenum alloy, etc.
Then, a photo-resist pattern is formed on the source/drain metal layer by photolithography using a second mask. In this case, a diffractive exposure mask having a diffractive exposing part at a channel portion of the thin film transistor is used as a second mask, thereby allowing the photo-resist pattern of the channel portion to have a lower height than the other source/drain pattern portion.
Subsequently, the source/drain metal layer is patterned by wet etching using the photo-resist pattern to thereby provide the source/drain metal pattern group including the data line 4, the source electrode 10, the drain electrode 12 being integral to the source electrode 10 and the upper storage electrode 22.
Next, the n+ amorphous silicon layer and the amorphous silicon layer are patterned at the same time by dry etching using the same photo-resist pattern to thereby provide the ohmic contact layer 50 and the active layer 48.
The photo-resist pattern having a relatively low height is removed from the channel portion by ashing and thereafter the source/drain metal pattern and the ohmic contact layer 50 of the channel portion are etched by dry etching. Thus, the active layer 48 of the channel portion is exposed to disconnect the source electrode 10 from the drain electrode 12.
Then, the photo-resist pattern left on the source/drain metal pattern group is removed by stripping.
Referring to FIG. 3C, the protective film 52 including the first to fifth contact holes 13, 21, 27, 33 and 39 are formed on the gate insulating film 46 provided with the source/drain metal pattern group by the third mask process.
More specifically, the protective film 52 is entirely provided on the gate insulating film 46 provided with the source/drain metal pattern group by a deposition technique such as PECVD. The protective film 52 is patterned by photolithography and etching using the third mask to thereby define the first to fifth contact holes 13, 21, 27, 33 and 39. The first contact hole 13 passes through the protective film 52 to expose the drain electrode 12, whereas the second contact hole 21 passes through the protective film 52 to expose the upper storage electrode 22. The third contact hole 27 passes through the protective film 52 and the gate insulating film 46 to expose the lower gate pad electrode 26. The fourth contact hole 32 passes through the protective film 52 to expose the lower data pad electrode 32. The fifth contact hole 30 passes through the protective film 52 and the gate insulating film 46 to expose the lower common pad electrode 38. Herein, if the source/drain metal is formed from a metal having a large dry-etching ratio such as molybdenum (Mo), then each of the first, second and fourth contact holes 13, 21 and 33 passes through the drain electrode 12, the upper storage electrode 22 and the lower data pad electrode 32 to thereby expose the side surfaces thereof.
The protective film 50 is formed from an inorganic material identical to the gate insulating film 46, or an organic material having a small dielectric constant such as an acrylic organic compound, BCB (benzocyclobutene) or PFCB (perfluorocyclobutane), etc.
Referring to FIG. 3D, a transparent conductive film pattern group including the pixel electrode 14, the upper gate pad electrode 28, the upper data pad electrode 34 and the upper common pad electrode 40 are provided on the protective film 52 by the fourth mask process.
More specifically, a transparent conductive film is coated onto the protective film 52 by a deposition technique such as sputtering, etc. Then, the transparent conductive film is patterned by photolithography and etching using a fourth mask to thereby provide the transparent conductive pattern group including the pixel electrode 14, the upper gate pad electrode 28, the upper data pad electrode 34 and the upper common pad electrode 40. The pixel electrode 14 is electrically connected, via the first contact hole 13, to the drain electrode 12 while being electrically connected, via the second contact hole 21, to the upper storage electrode 22. The upper gate pad electrode 28 is electrically connected, via the third contact hole 37, to the lower gate pad electrode 26. The upper data pad electrode 34 is electrically connected, via the fourth contact hole 33, to the lower data pad electrode 32. The upper common pad electrode 40 is electrically connected, via the fifth contact hole 39, to the lower common pad electrode 38.
Herein, the transparent conductive film is formed from indium-tin-oxide (ITO), tin-oxide (TO) or indium-zinc-oxide (IZO), etc.
The conventional thin film transistor substrate of horizontal electric field applying type and the fabricating method thereof as mentioned above uses four mask processes. However, since a technique using four mask processes remains complicated, the amount of cost reduction remains limited.